UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 671

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Figure 12-19. Example of Multiple Channel Conversion Operation (Hardware Trigger Mode): A/D Converter 0
(2) Operation of multiple channel conversion
Remark
(1) AD0CE bit = 1 (enable)
(2) Trigger specified by AD0TSEL.AD0TRGSEL11
(3) Signal of ANI01 pin is A/D-converted
(4) Conversion result is stored in AD0CR1 register
(5) Signal of ANI03 pin is A/D-converted
(6) Conversion result is stored in AD0CR3 register
AD0TSEL.AD0TRGSEL11 and
AD0TSEL.AD0TRGSEL10 bits
Note Two or more can be specified by the ADnCHEN register.
Remark
The signals of two or more analog input pins specified by the ADnCHEN register are sequentially converted,
starting from the pin with the lowest number, using a signal specified by the ADnTSEL.ADnTRGSEL11 and
ADnTSEL.ADnTRGSEL10 bits as a trigger.
corresponding to the analog input pin.
When conversion of the signals of all the specified analog input pins is completed, an A/Dn conversion end
interrupt request signal (INTADn) is generated. After completion of conversion, the A/D converter waits for the
trigger with the ADnSCM.ADnCE bit remaining set to 1.
This operation is suitable for an application where two or more analog input signals should be monitored when
the trigger is generated.
and AD0TSEL.AD0TRGSEL10 bits is generated (9) AD0SCM.AD0CS bit = 0
ANInk
ANInk
Analog Input Pin
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This is an operation example when the AD0SCM.AD0PLM, AD0TRG1, and AD0TRG0 bits = 001,
AD0CTL0.AD0MD1 and AD0CTL0.AD0MD0 bits = 00, and AD0CHEN register = 002AH.
Note
Note
However, A/D conversion is sequentially executed starting from the pin with the lowest number.
Trigger specified by
A/D converter 0: n = 0, k = 0 to 5
A/D converter 1: n = 1, k = 0 to 7
ADnCRk
ADnCRk
A/D Conversion Result Register
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CHAPTER 12 A/D CONVERTERS 0 AND 1
User’s Manual U18279EJ3V0UD
ANI00
ANI01
ANI02
ANI03
ANI04
ANI05
The result of conversion is stored in the ADnCRk register
(7) Signal of ANI05 pin is A/D-converted
(8) Conversion result is stored in AD0CR5 register
(10) INTAD0 interrupt request signal is generated
(11) Returns to (3) when the next trigger is input
(12) Set AD0CE bit to 0 to end (stop)
A/D converter 0
AD0CR0
AD0CR1
AD0CR2
AD0CR3
AD0CR4
AD0CR5
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