UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 922

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

extension codes are used here). During an INTIIC interrupt, the status is confirmed and the following steps are
executed.
920
The following shows an example of the processing of the slave device by an INTIIC interrupt (it is assumed that no
<1> When a stop condition is detected, communication is terminated.
<2> When a start condition is detected, the address is confirmed. If the address does not match, communication
<3> For data transmission/reception, when the ready flag is set, operation returns from the interrupt while the I
Remark
Interrupt servicing completed
is terminated. If the address matches, the communication mode is set and wait is released, and operation
returns from the interrupt (the ready flag is cleared).
bus remains in the wait status.
INTIIC occurred
<1> to <3> in the above correspond to <1> to <3> in Figure 17-20 Slave Operation Flowchart (2).
Set ready flag
SPD0 = 1?
STD0 = 1?
No
No
<3>
Figure 17-20. Slave Operation Flowchart (2)
Yes
Yes
Communication direction flag ← TRC0
<1>
<2>
User’s Manual U18279EJ3V0UD
Set communication mode flag
CHAPTER 17 I
Clear ready flag
COI0 = 1?
Yes
2
C BUS
No
and communication mode flag
direction flag, ready flag,
Clear communication
2
C