UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 985

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

can process a total of 89 to 96 interrupt requests.
occurrence is dependent on program execution.
sources.
generation of an exception event (i.e. fetching of an illegal opcode) (exception trap).
20.1 Features
The V850E/IF3 and V850E/IG3 are provided with a dedicated interrupt controller (INTC) for interrupt servicing and
An interrupt is an event that occurs independently of program execution, and an exception is an event whose
The V850E/IF3 and V850E/IG3 can process interrupt requests from the on-chip peripheral hardware and external
Interrupt sources are listed in Table 20-1.
Interrupts
• Non-maskable interrupts: 1 source (external: none, internal: 1 source)
• Maskable interrupts (the number of maskable interrupt sources differs depending on the product)
• 8 levels of programmable priorities (maskable interrupts)
• Multiple interrupt control according to priority
• Masks can be specified for each maskable interrupt request.
• Noise elimination, edge detection, and valid edge specification for external interrupt request signals.
Exceptions
• Software exceptions: 32 sources
• Exception traps:
V850E/IF3: 88 sources (external: 15 sources, internal: 73 sources)
V850E/IG3: 95 sources (external: 21 sources, internal: 74 sources)
Moreover, exception processing can be started by the TRAP instruction (software exception) or by
CHAPTER 20 INTERRUPT/EXCEPTION PROCESSING FUNCTION
2 sources (illegal opcode exception and debug trap)
User’s Manual U18279EJ3V0UD
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