UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 814

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

16.4 Control Registers
812
The following registers are used to control CSIBn.
• CSIBn control register 0 (CBnCTL0)
• CSIBn control register 1 (CBnCTL1)
• CSIBn control register 2 (CBnCTL2)
• CSIBn status register (CBnSTR)
(1) CSIBn control register 0 (CBnCTL0)
CBnCTL0 is a register that controls the CSIBn serial transfer operation.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 01H.
Note These bits can only be rewritten when the CBnPWR bit = 0. However, CBnPWR bit = 1 can also be
Caution Be sure to set bits 3 and 2 to “0”.
(n = 0 to 2)
set at the same time as rewriting these bits.
CBnCTL0
After reset: 01H
CBnPWR
CBnRXE
CBnPWR
CBnTXE
• The CBnPWR bit controls the CSIBn operation and resets the internal circuit.
• The SOBn output is low level when the CBnTXE bit is 0.
• When the CBnRXE bit is cleared to 0, no reception end interrupt is output even
when the prescribed data is transferred in order to disable the receive operation,
and the receive data (CBnRX register) is not updated.
< >
0
1
0
1
0
1
CHAPTER 16 CLOCKED SERIAL INTERFACE B (CSIB)
Note
Note
R/W
CBnTXE
Disable CSIBn operation and reset the CBnSTR register
Enable CSIBn operation
Disable transmit operation
Enable transmit operation
Disable receive operation
Enable receive operation
< >
Note
Address: CB0CTL0 FFFFFD00H, CB1CTL0 FFFFFD10H,
User’s Manual U18279EJ3V0UD
CBnRXE
Specification of transmit operation disable/enable
Specification of receive operation disable/enable
Specification of CSIBn operation disable/enable
< >
CB2CTL0 FFFFFD20H
Note
CBnDIR
< >
Note
0
0
CBnTMS
Note
CBnSCE
< >
(1/2)