UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 1011

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

20.3.7 Maskable interrupt status flag (ID)
disabling of interrupt requests. The ID flag is allocated to the PSW.
The ID flag controls the maskable interrupt’s operating state, and stores control information regarding enabling or
Reset sets this flag to 00000020H.
Note Interrupt disable flag (ID) function
After rest: 00000020H
PSW
ID is set (1) by the DI instruction and cleared (0) by the EI instruction. Its value is also modified by the
RETI instruction or LDSR instruction when referencing the PSW.
Non-maskable interrupt request signals and exceptions are acknowledged regardless of this flag. When
a maskable interrupt request signal is acknowledged, the ID flag is automatically set (1) by hardware.
An interrupt request signal generated during the acknowledgment disabled period (ID flag = 1) can be
acknowledged when the xxICn.xxIFn bit is set (1), and the ID flag is cleared (0).
ID
0
1
CHAPTER 20 INTERRUPT/EXCEPTION PROCESSING FUNCTION
Maskable interrupt request signal acknowledgment enabled
Maskable interrupt request signal acknowledgment disabled (pending)
0
User’s Manual U18279EJ3V0UD
Maskable interrupt servicing specification
NP EP
ID SAT CY OV
Note
S
Z
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