UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 868

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

866
Condition for clearing (ACKD0 bit = 0)
• When a stop condition is detected
• At the rising edge of the next byte’s first clock
• Cleared by the LREL0 bit = 1 (exit from communications)
• When the IICE0 bit changes from 1 to 0 (operation stop)
• Reset
Condition for clearing (STD0 bit = 0)
• When a stop condition is detected
• At the rising edge of the next byte’s first clock following
• Cleared by the LREL0 bit = 1 (exit from communications)
• When the IICE0 bit changes from 1 to 0 (operation stop)
• Reset
Condition for clearing (SPD0 bit = 0)
• At the rising edge of the address transfer byte’s first
• When the IICE0 bit changes from 1 to 0 (operation stop)
• Reset
ACKD0
address transfer
clock following setting of this bit and detection of a start
condition
STD0
SPD0
0
1
0
1
0
1
ACK was not detected.
ACK was detected.
Start condition was not detected.
Start condition was detected. This indicates that the address transfer period is in effect
Stop condition was not detected.
Stop condition was detected. The master device’s communication is terminated and the bus is released.
User’s Manual U18279EJ3V0UD
CHAPTER 17 I
Detection of start condition
Detection of stop condition
Detection of ACK
Condition for setting (ACKD0 bit = 1)
• After the SDA pin is set to low level at the rising edge of
Condition for setting (STD0 bit = 1)
• When a start condition is detected
Condition for setting (SPD0 bit = 1)
• When a stop condition is detected
the SCL pin’s ninth clock
2
C BUS
(3/3)