UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 786
UPD70F3451GC-UBT-A
Manufacturer Part Number
UPD70F3451GC-UBT-A
Description
MCU 32BIT 128KB FLASH 80LQFP
Manufacturer
Renesas Electronics America
Series
V850E/Ix3r
Datasheet
1.UPD70F3451GC-UBT-A.pdf
(1191 pages)
Specifications of UPD70F3451GC-UBT-A
Core Processor
RISC
Core Size
32-Bit
Speed
64MHz
Connectivity
CSI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
44
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3.5 V ~ 5.5 V
Data Converters
A/D 10x12b, 4x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Manufacturer
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Part Number:
UPD70F3451GC-UBT-A
Manufacturer:
Renesas Electronics America
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15.7.6 Parity types and corresponding operation
transmission and reception sides.
784
A parity bit is used to detect a bit error in communication data. Normally, the same type of parity bit is used at the
(1) Even parity
(2) Odd parity
(3) 0 parity
(4) No parity
(a) During transmission
(b) During reception
(a) During transmission
(b) During reception
During transmission the parity bit is set to “0” regardless of the transmit data.
During reception, no parity bit check is performed. Therefore, no parity error is generated regardless of
whether the parity bit is “0” or “1”.
No parity bit is added to the transmit data.
During reception, the receive operation is performed as if there were no parity bit. Since there is no parity bit,
no parity error is generated.
• If the number of bits with the value “1” within the transmit data is odd: 1
• If the number of bits with the value “1” within the transmit data is even: 0
• If the number of bits with the value “1” within the transmit data is odd: 0
• If the number of bits with the value “1” within the transmit data is even: 1
The parity bit is controlled so that the number of bits with the value “1” within the transmit data including
the parity bit is even. The parity bit value is as follows.
The number of bits with the value “1” within the receive data including the parity bit is counted, and a
parity error is generated if this number is odd.
In contrast to even parity, the parity bit is controlled so that the number of bits with the value “1” within the
transmit data including the parity bit is odd. The parity bit value is as follows.
The number of bits with the value “1” within the receive data including the parity bit is counted, and a
parity error is generated if this number is even.
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE B (UARTB)
User’s Manual U18279EJ3V0UD
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