UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 737

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

14.6.5 Reception errors
reception result error flags are set in the UAnSTR register and a reception error interrupt request signal (INTUAnRE)
is output when an error occurs.
Errors during a receive operation are of three types: parity errors, framing errors, and overrun errors. Data
It is possible to ascertain which error occurred during reception by reading the contents of the UAnSTR register.
Clear the reception error flag by writing 0 to it after reading it.
Caution The reception end interrupt request signal (INTUAnR) and reception error interrupt request
Remark
• Reception error causes
UAnPE
UAnFE
UAnOVE
Error Flag
signal (INTUAnRE) are not generated simultaneously. The INTUAnR signal is generated when a
reception ends normally. The INTUAnRE signal is generated and the INTUAnR signal is not
generated when a reception error occurs.
n = 0 to 2
Parity error
Overrun error
Framing error
Reception Error
CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE A (UARTA)
Received parity bit does not match the setting
Stop bit not detected
Reception of next data ended before data was read from UAnRX register
User’s Manual U18279EJ3V0UD
Cause
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