UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 391

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(b) Pulse width measurement with capture register
When pulse width measurement is performed with the TABnCCRa register used as a capture register,
software processing is necessary for reading the capture register each time the INTTBnCCa signal has
been detected and for calculating an interval.
TABnCCR0 register
TABnCCR1 register
TABnCCR2 register
TABnCCR3 register
INTTBnCC0 signal
INTTBnCC1 signal
INTTBnCC2 signal
INTTBnCC3 signal
INTTBnOV signal
TIBn0 pin input
TIBn1 pin input
TIBn2 pin input
TIBn3 pin input
16-bit counter
TABnOVF bit
TABnCE bit
FFFFH
0000H
CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB)
Pulse interval
(D
Pulse interval
20
(D
Pulse interval
Pulse interval
0000
0000
0000
0000
00
+ 1)
(D
(D
+ 1)
D
30
10
20
D
+ 1)
+ 1)
00
D
User’s Manual U18279EJ3V0UD
Pulse interval
30
D
Pulse interval
(10000H +
D
(10000H +
10
01
D
D
Pulse interval
CLR instruction
Cleared to 0 by
21
Pulse interval
00
(10000H +
− D
D
(10000H +
11
D
− D
D
00
31
D
− D
D
20
)
01
20
10
D
− D
)
10
30
)
D
30
Pulse interval
11
)
D
(10000H +
D
Pulse interval
21
02
(10000H +
D
D
D
− D
12
31
01
− D
Cleared to 0 by
CLR instruction
D
01
Pulse interval
11
)
(10000H +
D
11
D
)
32
12
Pulse interval
D
D
− D
(20000H +
Pulse interval
31
02
D
(D
22
31
Pulse interval
D
D
13
D
)
− D
(10000H +
21
D
12
32
− D
D
03
21
13
D
− D
12
)
CLR instruction
Cleared to 0 by
02
)
Pulse interval
02
(10000H +
D
)
D
33
03
D
Pulse interval
− D
D
22
(D
32
32
23
D
D
)
13
− D
D
33
D
22
D
23
22
03
)
D
33
D
23
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