UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 806

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

15.10 Cautions
804
Cautions concerning UARTB are shown below.
(1) When supply clock to UARTB is stopped
(2) Caution on setting UBCTL0 register
(3) Caution on setting UBFIC2 register
(4) Transmission interrupt request signal
(5) Initialization during continuous transmission in single mode
(6) Initialization during continuous transmission (pending mode) in FIFO mode
(7) Initialization during continuous transmission (pointer mode) in FIFO mode
When the supply of clocks to UARTB is stopped (for example, IDLE and STOP modes), operation stops with
each register retaining the value it had immediately before the supply of clocks was stopped. The TXDB pin
output also holds and outputs the value it had immediately before the supply of clocks was stopped.
However, operation is not guaranteed after the supply of clocks is restarted. Therefore, after the supply of
clocks is restarted, the circuits should be initialized by setting the UBPWR bit = 0, UBRXE bit = 0, and UBTXE
bit = 0.
• When using UARTB, set the external pins related to the UARTB function to the alternate function and set
• Be sure to input a high level to the RXDB pin when setting the external pins related to the UARTB function
Be sure to clear the UBCTL0.UBTXE bit (to disable transmission) and UBCTL0.UBRXE bit (to disable
reception) to 0 before writing data to the UBFIC2 register. If data is written to the UBFIC2 register with the
UBTXE or UBRXE bit set to 1, the operation is not guaranteed.
In the single mode, the transmission enable interrupt request signal (INTUBTIT) occurs when the UBTX
register becomes empty (when 1 byte of data is transferred from the UBTX register to the transmit shift
register). In the FIFO mode, the FIFO transmission end interrupt request signal (INTUBTIF) occurs when
data is no longer in transmit FIFO and the transmit shift register (when the FIFO and register are empty).
However, the INTUBTIT signal or INTUBTIF signal does not occur if the transmit data register becomes
empty due to RESET input.
Confirm that the UBSTR.UBTSF bit is 0 before executing initialization during transmission processing. If
initialization is executed while the UBTSF bit is 1, the transmit data is not guaranteed.
Confirm that the UBSTR.UBTSF bit is 0 before executing initialization during transmission processing (this
can also be done by checking the FIFO transmission end interrupt request signal (INTUBTIF)). If initialization
is executed while the UBTSF bit is 1, the transmit data is not guaranteed.
To write transmit data to transmit FIFO by DMA control, set the number of transmit data specified as the
trigger by the UBFIC2.UBTT3 to UBFIC2.UBTT0 bits to 1 byte; otherwise the operation will not be
guaranteed.
Confirm that the UBSTR.UBTSF bit is 0 before executing initialization during transmission processing (this
can also be done by checking the FIFO transmission end interrupt request signal (INTUBTIF)). If initialization
is executed while the UBTSF bit is 1, the transmit data is not guaranteed.
the UBCTL2 register. Then set the UBCTL0.UBPWR bit to 1 before setting the other bits.
to the alternate function.
UBCTL0.UBRXE bit has been set to 1, and reception may be started.
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE B (UARTB)
If a low level is input, it is judged that a falling edge is input after the
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