UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 867

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Note The IICS0.TRC0 bit is cleared to 0 and the SDA line become high impedance when the IICC0.WREL0
Condition for clearing (TRC0 bit = 0)
• When a stop condition is detected
• Cleared by the LREL0 bit = 1 (exit from communications)
• When the IICE0 bit changes from 1 to 0 (operation stop)
• Cleared by the IICC0.WREL0 bit = 1
• When the ALD0 bit changes from 0 to 1 (arbitration loss)
• Reset
Master
• When “1” is output to the first byte’s LSB (transfer
Slave
• When a start condition is detected
When not used for communication
Condition for clearing (EXC0 bit = 0)
• When a start condition is detected
• When a stop condition is detected
• Cleared by the LREL0 bit = 1 (exit from communications)
• When the IICE0 bit changes from 1 to 0 (operation stop)
• Reset
Condition for clearing (COI0 bit = 0)
• When a start condition is detected
• When a stop condition is detected
• Cleared by the LREL0 bit = 1 (exit from communications)
• When the IICE0 bit changes from 1 to 0
• Reset
direction specification bit)
TRC0
EXC0
COI0
0
1
0
1
0
1
bit is set to 1 and wait state is released at the ninth clock with the TRC0 bit = 1.
Extension code was not received.
Extension code was received.
Addresses do not match.
Addresses match.
Receive status (other than transmit status). The SDA line is set for high impedance.
Transmit status. The value in the SO latch is enabled for output to the SDA line (valid starting at the rising
edge of the first byte’s ninth clock).
Note
(wait release)
User’s Manual U18279EJ3V0UD
Detection of extension code reception
CHAPTER 17 I
Detection of transmit/receive status
Detection of matching addresses
Condition for setting (EXC0 bit = 1)
• When the higher four bits of the received address data
Condition for setting (COI0 bit = 1)
• When the received address matches the local address
Condition for setting (TRC0 bit = 1)
Master
• When a start condition is generated
• When “0” is output to the first byte’s LSB (transfer
Slave
• When “1” is input in the first byte’s LSB (transfer
is either “0000” or “1111” (set at the rising edge of the
eighth clock).
(SVA0 register) (set at the rising edge of the eighth
clock).
direction specification bit)
direction specification bit)
2
C BUS
(2/3)
865