UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 335

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

7.6.2
TABnCTL0.TABnCE bit is set to 1, and an interrupt request signal (INTTBnCC0) is generated each time the specified
number of edges set by the TABnCCR0 register have been counted. The TOBn0 to TOBn3 pins cannot be used.
When using the TOBn0 to TOBn3 pins for external event count input, set the TABnCTL1.TABnEEE bit to 1 in the
interval timer mode (see 7.6.1 (3) Operation by external event count input (EVTBn)).
TABnCCR0 register
In the external event count mode, the valid edge of the external event count input (EVTBn) is counted when the
The TABnCCR1 to TABnCCR3 registers are not used in the external event count mode.
Remark
INTTBnCC0 signal
Remarks 1. This figure shows the basic timing when the rising edge is specified as the valid edge of the
EVTBn pin
(external event
count input)
16-bit counter
External event count mode (TABnMD2 to TABnMD0 bits = 001)
TABnCE bit
FFFFH
2. n = 0, 1
n = 0, 1
0000H
external event count input.
detector
External
event
count:
(D
Edge
Figure 7-13. Configuration in External Event Count Mode
Figure 7-14. Basic Timing in External Event Count Mode
0
CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB)
D
+ 1)
0
TABnCE bit
External
event
count:
(D
0
D
D
+ 1)
0
0
User’s Manual U18279EJ3V0UD
External
event
count:
(D
0
D
+ 1)
0
CCR0 buffer register
TABnCCR0 register
16-bit counter
TABnCCR0 register
INTTBnCC0 signal
(EVTBn pin input)
Clear
External event
16-bit counter
Match signal
count input
D
0
− 1
D
INTTBnCC0 signal
D
0
0
0000
0001
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