UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 419

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(7) TMTm I/O control register 3 (TTmIOC3)
Note V850E/IG3 only
The TTmIOC3 register is an 8-bit register that controls the encoder clear function operation.
The TTmIOC3 register is valid only in the encoder compare mode.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
V850E/IF3
V850E/IG3
m = 1
m = 0, 1
TTmIOC3
After reset: 00H
TTmSCE
TTmSCE
• Clears 16-bit counter to 0000H when valid edge of TECRm pin specified by the
• Clears 16-bit counter to 0000H when clear level conditions of the TTmZCL,
• Setting of the TTmZCL, TTmBCL, and TTmACL bits is valid and that of the
• Setting of the TTmZCL, TTmBCL, and TTmACL bits is invalid and setting of
• Be sure to set the TTmCTL2.TTmUDS1 and TTmCTL2.TTmUDS0 bits to 10 or 11
TTmZCL
Setting of the
TTmBCL
Setting of the
TTmACL
Setting of the
TTmECS1 and TTmECS0 bits is detected when the TTmSCE bit = 0.
TTmBCL, and TTmACL bits match input levels of the TECRm, TENCm1, and
TENCm0 pins when TTmSCE bit = 1.
TTmECS1 and TTmECS0 bits is invalid when the TTmSCE bit = 1.
Encoder clear interrupt request signal (INTTIECm) is not generated.
the TTmECS1 and TTmECS0 bits is valid when the TTmSCE bit = 0.
The INTTIECm signal is generated when valid edge specified by the TTmECS1
and TTmECS0 bits is detected.
when the TTmSCE bit = 1.
Operation is not guaranteed if the TTmUDS1 and TTmUDS0 bits = 00 or 01 and
the TTmSCE bit = 1.
CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT)
0
1
0
1
0
1
0
1
7
R/W
TTmZCL TTmBCL TTmACL TTmECS1TTmECS0 TTmEIS1 TTmEIS0
Clears 16-bit counter on detection of edge of encoder clear signal (TECRm pin).
Clears 16-bit counter on detection of clear level condition of the TENCm0,
TENCm1, and TECRm pins.
Clears low level of the
Clears high level of the
Clears low level of the
Clears high level of the
Clears low level of the
Clears high level of the
TTmZCL
TTmBCL
TTmACL
6
Address: TT0IOC3 FFFFF586H
Clear level selection of encoder input signal (TENCm1 pin)
Clear level selection of encoder input signal (TENCm0 pin)
Clear level selection of encoder clear signal (TECRm pin)
User’s Manual U18279EJ3V0UD
bit is valid only when the
bit is valid only when the
bit is valid only when the
5
TECRm pin.
TENCm1 pin.
TENCm0 pin.
TECRm pin.
TENCm1 pin.
TENCm0 pin.
Encoder clear selection
4
3
TTmSCE
TTmSCE
TTmSCE
Note
, TT1IOC3 FFFFF5C6H
2
bit = 1.
bit = 1.
bit = 1.
1
0
(1/2)
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