UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 683

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

12.6.5 Operation in standby mode
12.6.6 Timing of accepting trigger in conversion channel specification mode and extension buffer mode
it is generated again, until the A/Dn conversion end interrupt signal (INTADn) is generated after A/D conversion is
started by the first generation of selection trigger 1 or 2. In the extension buffer mode, the error flag is set to 1 in
accordance with a specified error condition if selection trigger 1 or 2, or selection load trigger 1 or 2 is generated
during this period (except, however, the case in Caution 2 in 12.4.11 (1) Error detection function).
12.6.7 Variation of A/D conversion results
by noise. To reduce the variation, take counteractive measures with the program, such as by averaging the A/D
conversion results.
12.6.8 A/D conversion result hysteresis characteristics
and then perform A/D conversion. After the A/D conversion has finished, the analog input voltage remains in the
internal sample & hold capacitor. As a result, the following phenomena may occur if the output impedance from the
analog input source is too high.
A/D conversion twice consecutively on the same channel, and discard the first conversion result.
(1) HALT mode
(2) IDLE mode and STOP mode
In the conversion channel specification mode and extension buffer mode, selection trigger 1 or 2 is ignored, even if
Remark
The results of the A/D conversion may vary depending on the fluctuation of the supply voltage, or may be affected
Successive comparison type A/D converters hold an analog input voltage in an internal sample & hold capacitor
• When the same channel is used for A/D conversions, if the voltage is higher or lower than the previous A/D
• When switching the analog input channel, hysteresis characteristics may appear where the conversion result is
To obtain more accurate conversion results, lower the output impedance from the analog input source or execute
conversion, then hysteresis characteristics may appear where the conversion result is affected by the previous
value. Even if the conversion were to be performed at the same potential, the results may thus vary.
affected by the previous channel value. This is because one A/D converter is used for the A/D conversions.
Even if the conversion were to be performed at the same potential, the results may thus vary.
Remark
The A/D conversion operation continues. If the HALT mode is released by a maskable interrupt request signal
that is not masked, the values of the ADnSCM, ADnCRm, and ADnECRa registers are held.
No conversion operation is performed because clock supply to A/D converters 0 and 1 is stopped.
Be sure to set the ADnSCM.ADnCE bit to 0 when the IDLE or STOP mode is set. At this time, setting the A/D
power save mode (ADnSCM.ADnPS bit = 0) is recommended.
n = 0, 1
n = 0, 1
m = 0 to 15
CHAPTER 12 A/D CONVERTERS 0 AND 1
User’s Manual U18279EJ3V0UD
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