UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 190

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

188
(3) When releasing STOP mode by interrupt request
PLL output clock
STOP status
OST counter
<1> When the STOP mode is set, both the oscillator and PLL stop.
<2> When the STOP mode is released, the oscillator is activated and the OST counter starts counting the
<3> When half the oscillation stabilization time set to the OSTS has elapsed, PLL starts operating. The
<4> After half the oscillation stabilization time has elapsed, the lockup wait time starts. The remaining
<5> When the lockup time of PLL is over, clock supply to the internal circuitry is started. At this time, the
<6> The operation to be performed when the STOP mode is released by a reset signal (RESET pin input,
V
DD0
, V
At this time, PLL is stopped in the STOP mode. The OST counter is initialized.
oscillation stabilization time. At this time, PLL remains stopped.
clock generated by the oscillator must be stabilized before PLL starts operating.
oscillation stabilization time is “1/2 the oscillation stabilization time”. Take this into consideration
when setting a value to the OSTS register.
count time of the OST counter is the lockup wait time.
status before the STOP mode was set is recovered.
reset signal (LVIRES) generation by the low-voltage detector (LVI), reset signal (POCRES)
generation by the power-on-clear circuit (POC)) is the same as that in (1) Power on (power-on
reset) and (2) Reset input with power on.
f
DD1
CPU
X1
H
00H (initialization)
In STOP mode
<1>
CHAPTER 5 CLOCK GENERATOR
STOP mode released
clock from oscillator
is 1/2 of set value of
User’s Manual U18279EJ3V0UD
stabilization time of
Fixed oscillation
OSTS register
<2>
<3>
PLL lockup time is
1/2 of set value of
OSTS register
<4>
Status before STOP mode was set is
resumed after release of STOP mode
<5> <6>
PLL output stabilized
00H
The actual