UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 724

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UPD70F3451GC-UBT-A

Manufacturer Part Number
UPD70F3451GC-UBT-A
Description
MCU 32BIT 128KB FLASH 80LQFP
Manufacturer
Renesas Electronics America
Series
V850E/Ix3r
Datasheet

Specifications of UPD70F3451GC-UBT-A

Core Processor
RISC
Core Size
32-Bit
Speed
64MHz
Connectivity
CSI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
44
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3.5 V ~ 5.5 V
Data Converters
A/D 10x12b, 4x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3451GC-UBT-A
Manufacturer:
Renesas Electronics America
Quantity:
10 000
722
(1) UARTAn control register 0 (UAnCTL0)
(2) UARTAn control register 1 (UAnCTL1)
(3) UARTAn control register 2 (UAnCTL2)
(4) UARTAn option control register 0 (UAnOPT0)
(5) UARTAn status register (UAnSTR)
(6) UARTAn receive shift register
(7) UARTAn receive data register (UAnRX)
(8) UARTAn transmit shift register
(9) UARTAn transmit data register (UAnTX)
The UAnCTL0 register is an 8-bit register used to specify the UARTAn operation.
The UAnCTL1 register is an 8-bit register used to select the base clock (f
The UAnCTL2 register is an 8-bit register used to control the baud rate for the UARTAn.
The UAnOPT0 register is an 8-bit register used to control serial transfer for the UARTAn.
The UAnSTR register consists of flags indicating the error contents when a reception error occurs. Each one
of the reception error flags is set (to 1) upon occurrence of a reception error.
This is a shift register used to convert the serial data input to the RXDAn pin into parallel data. Upon reception
of 1 byte of data and detection of the stop bit, the receive data is transferred to the UAnRX register.
This register cannot be manipulated directly.
The UAnRX register is an 8-bit register that holds receive data. When 7 characters are received, 0 is stored in
the highest bit (when data is received LSB first).
In the reception enabled status, receive data is transferred from the UARTAn receive shift register to the
UAnRX register in synchronization with the completion of shift-in processing of 1 frame.
Transfer to the UAnRX register also causes the reception end interrupt request signal (INTUAnR) to be output.
The UARTAn transmit shift register is a shift register used to convert the parallel data transferred from the
UAnTX register into serial data.
When 1 byte of data is transferred from the UAnTX register, the UARTAn transmit shift register data is output
from the TXDAn pin.
This register cannot be manipulated directly.
The UAnTX register is an 8-bit transmit data buffer. Transmission starts when transmit data is written to the
UAnTX register. When data can be written to the UAnTX register (when data of one frame is transferred from
the UAnTX register to the UARTAn transmit shift register), the transmission enable interrupt request signal
(INTUAnT) is generated.
CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE A (UARTA)
User’s Manual U18279EJ3V0UD
UCLK
) for the UARTAn.

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