UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 237

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

counts each time the valid edge of external event count input is detected.
TAAmCCR0 register is transferred to the CCR0 buffer register.
cleared to 0000H, and a compare match interrupt request signal (INTTAmCC0) is generated.
“value set to TAAmCCR0 register + 1” times.
When the TAAmCE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H. The counter
When the count value of the 16-bit counter matches the value of the CCR0 buffer register, the 16-bit counter is
The INTTAmCC0 signal is generated each time the valid edge of the external event count input has been detected
TAAmCTL0
TAAmCTL1
TAAmIOC2
(a) TAAm control register 0 (TAAmCTL0)
(b) TAAm control register 1 (TAAmCTL1)
(c) TAAm I/O control register 2 (TAAmIOC2)
(d) TAAm counter read buffer register (TAAmCNT)
(e) TAAm capture/compare register 0 (TAAmCCR0)
The count value of the 16-bit counter can be read by reading the TAAmCNT register.
If the TAAmCCR0 register is set to D
reached (D
TAAaSYE
TAAmCE
Figure 6-19. Register Setting for Operation in External Event Count Mode (1/2)
0/1
0
0
0
+ 1) and the compare match interrupt request signal (INTTAmCC0) is generated.
TAAmEST
0
0
0
CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA)
TAAmEEE
0
0
0
User’s Manual U18279EJ3V0UD
0
0
0
0
, the count is cleared when the number of external events has
TAAmEES1
0/1
0
0
TAAmEES0 TAAmETS1 TAAmETS0
TAAmCKS2 TAAmCKS1 TAAmCKS0
TAAmMD2 TAAmMD1 TAAmMD0
0/1
0
0
0
0
0
Additionally, the set value of the
0
0
1
Select valid edge
of external event
count input (TIAm0 pin)
0: Stop counting
1: Enable counting
0, 0, 1:
External event count mode
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