UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 980

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

19.8 Next Address Setting Function
master register and a slave register (n = 0 to 3).
immediately before.
are automatically updated to the new value after completion of transfer
(period) of setting.
978
The DSAnH, DSAnL, DDAnH, DDAnL, and DBCn registers are two-stage FIFO buffer registers consisting of a
When the terminal count is issued, these registers are automatically rewritten with the value that was set
If new DMA transfer setting is made to these registers during DMA transfer, therefore, the values of the registers
Note To make new DMA transfer setting, confirm that DMA transfer has been started. If a new setting is made
Figure 19-8 shows the configuration of the buffer register.
The actual DMA transfer is executed in accordance with the contents of the slave register.
The set value to be reflected upon the master register and slave register differs as follows, depending on the timing
(1) Period from system reset to the generation of the first DMA transfer request
(2) During DMA transfer (period from the generation of DMA transfer request to completion of DMA
(3) Period from completion of DMA transfer to start of next DMA transfer
Remark
The set values are reflected on both the master and slave registers.
transfer)
The set value is reflected only on the master register and not on the slave register (the slave register holds the
set value for the next DMA transfer).
After completion of DMA transfer, however, the contents of the master register are automatically overwritten to
the slave register.
If the value of a register is read during this period, the value of the slave register is read.
To check that DMA transfer has been started, confirm that the first transfer has been executed by reading the
DBCn register (n = 0 to 3).
The set value is reflected on both the master and slave registers.
before the start of DMA transfer, the set value is overwritten to both the master and slave registers.
“Completion of DMA transfer” means either of the following cases.
• End of DMA transfer (terminal count)
• Forced termination of DMA transfer (setting DCHCn.INITn bit to 1).
Data read
Data write
CHAPTER 19 DMA FUNCTIONS (DMA CONTROLLER)
Figure 19-8. Buffer Register Configuration
register
Master
User’s Manual U18279EJ3V0UD
register
Slave
Note
.
controller
Address/
count