UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 182

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

180
(3) Power save control register (PSC)
Notes 1. For details, see Table 20-1 Interrupt Source List.
Cautions 1. Be sure to set bits 0, 2, 3, and 5 to 7 to “0”.
The PSC register is an 8-bit register that controls the standby function and specifies the standby mode by
setting the STB bit. The PSC register is a special register (see 3.4.8 Special registers). Data can be written
to this register only in a combination of specific sequences.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
2. Setting is valid only in the IDLE mode and STOP mode.
2. Before setting a standby mode by setting the STB bit to 1, be sure to set the PCC register
3. To set the IDLE mode or STOP mode, set the PCC register to 03H, and the PSMR.PSM0 bit
After reset:
PSC
to 03H and then set the STB bit to 1. Otherwise, the standby mode may not be set or
released. After releasing the standby mode, change the value of the PCC register to the
desired value.
in that order and then set the STB bit to 1.
INTM
STB
00H
0
1
0
1
0
Standby mode release by INTxx request enabled
Standby mode release by INTxx request disabled
Normal mode
Standby mode
R/W
Standby mode control
0
CHAPTER 5 CLOCK GENERATOR
Address:
User’s Manual U18279EJ3V0UD
0
FFFFF1FEH
INTM
< >
Note 2
Sets operation mode
by maskable interrupt request (INTxx
0
0
STB
< >
Note 1
0
)