UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 981

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

19.9 DMA Transfer Start Factors
There are two types of DMA transfer start factors, as shown below.
Cautions 1. Do not use both start factors ((1) and (2)) in combination for the same channel (if both start
(1) Transfer start triggered by software
(2) Transfer start triggered by request from on-chip peripheral I/O
If the DCHCn.STGn, DCHCn.Enn, and DCHCn.TCn bits are set as follows, DMA transfer is started by software
request (n = 0 to 3).
• STGn bit = 1
• Enn bit = 1
• TCn bit = 0
If, when the DCHCn.Enn and DCHCn.TCn bits are set as shown below, an interrupt request is issued from the
on-chip peripheral I/O that is set in the DTFRn register, DMA transfer starts (n = 0 to 3).
• Enn bit = 1
• TCn bit = 0
2. If DMA transfer is started via software and if the software does not correctly detect whether
factors are generated at the same time, only one of them is valid, but the valid start factor
cannot be identified).
The operation is not guaranteed if both start factors are used in combination.
the expected DMA transfer operation has been ended through manipulation (setting to 1) of
the DCHCn.STGn bit, it cannot be guaranteed whether the next (second) manipulation of the
STGn bit corresponds to the start of “the next DMA transfer expected by software” (n = 0 to
3).
For example, suppose single transfer is started by manipulating the STGn bit. Even if the
STGn bit is manipulated next (the second time) without checking by software whether the
single transfer has actually been executed, the next (second) DMA transfer is not always
executed. This is because the STGn bit may be manipulated the second time before the first
DMA transfer is started or ended because, for example, DMA transfer with a higher priority
had already been started when the STGn bit was manipulated for the first time.
It is therefore necessary to manipulate the STGn bit the next time (the second time) after
checking whether DMA transfer started by the first manipulation of the STGn bit has been
ended.
End of DMA transfer can be checked by checking the contents of the DBCn register.
CHAPTER 19 DMA FUNCTIONS (DMA CONTROLLER)
User’s Manual U18279EJ3V0UD
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