UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 635

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(6) A/D converter n trigger select register (ADnTSEL)
Note
Caution
The ADnTSEL register is a register that specifies trigger in the hardware trigger mode and conversion channel
specification mode, and trigger (selection trigger 1, selection trigger 2, selection load trigger 1, and selection
load trigger 2) in the extension buffer mode.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 10H.
Be sure to set bits 3, 5, and 7 to “0” and set bit 4 to “1” in the hardware trigger mode and conversion
channel specification mode.
Set the ADnTSEL register when the ADnSCM.ADnCE bit = 0 (conversion operation is
stopped) (the same value can be written to the register when the ADnCE bit = 1 (conversion
operation is enabled)).
ADnTSEL
(n = 0, 1)
After reset: 10H
ADnTRGSEL11 ADnTRGSEL10
LDTSEL2
ADnTRGSEL21
ADnLDTSEL2
ADnLDTSEL1
ADn
0
1
0
0
1
1
0
1
0
0
1
1
Note
Note
Note
Note
R/W
ADnTRGSEL20
Specification of selection load trigger 1 for ADnECR0 to ADnECR2 registers
Specification of selection load trigger 2 for ADnECR3, ADnECR4 registers
LDTRG1
LDTRG2
LDTRG1
LDTRG2
CHAPTER 12 A/D CONVERTERS 0 AND 1
0
1
0
1
0
1
0
1
0
Address: AD0TSEL FFFFF231H, AD1TSEL FFFFF2B1H
Note
Specification of selection trigger 2 for ADnECR3, ADnECR4 registers
User’s Manual U18279EJ3V0UD
•
•
TRGSEL21
ITRG1
ITRG2
ITRG3
ITRG4
ITRG1
ITRG2
ITRG3
ITRG4
In hardware trigger mode or conversion channel specification mode:
Trigger specification
In expansion buffer mode:
Specification of selection trigger 1 for ADnECR0 to ADnECR2 registers
ADn
Note
TRGSEL20
ADn
Note
LDTSEL1
ADn
Note
0
TRGSEL11
ADn
TRGSEL10
ADn
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