UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 695

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(2) A/D converter 2 mode register 1 (AD2M1)
AD2FR3
Cautions 1. See Table 13-2 Setting Example During Conversion Mode for the AD2FR3 to AD2FR0 bits.
0
0
0
0
0
0
0
1
1
Caution Set the A/D conversion time in a range from 3.8 to 10
Remark
The AD2M1 register is a register that specifies the number of A/D conversion clocks and A/D conversion time.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
Note The number of clocks (f
AD2FR2
2. Changing the AD2FR3 to AD2FR0 bits is prohibited during conversion operation (AD2CE
3. Be sure to set bits 4 to 7 to “0”.
AD2M1
0
0
0
1
1
1
1
0
0
After reset: 00H
bit = 1).
f
AD2
: Operating clock of A/D converter 2
AD2FR1
Other than above
0
1
1
0
0
1
1
0
0
0
Table 13-2. Setting Example During Conversion Mode
AD2FR0
R/W
1
0
1
0
1
0
1
0
1
AD2
0
Address: FFFFFB81H
) from the start to the end of A/D conversion.
CHAPTER 13 A/D CONVERTER 2
62
93
124
155
186
217
248
279
310
Conversion Clocks
User’s Manual U18279EJ3V0UD
Number of A/D
0
0
Note
AD2FR3 AD2FR2 AD2FR1 AD2FR0
62/f
93/f
124/f
155/f
186/f
217/f
248/f
279/f
310/f
Setting prohibited
A/D Conversion
AD2
AD2
AD2
AD2
AD2
AD2
AD2
AD2
AD2
Time
μ
s.
Setting prohibited
Setting prohibited
3.88
4.84
5.81
6.78
7.75
8.72
9.69
(f
f
AD2
XX
μ
μ
μ
μ
μ
μ
μ
= 64 MHz)
= 32 MHz
s
s
s
s
s
s
s
Setting prohibited
3.86
5.17
6.46
7.75
9.04
Setting prohibited
Setting prohibited
Setting prohibited
f
(f
AD
XX
2 = 24 MHz
μ
μ
μ
μ
μ
= 48 MHz)
s
s
s
s
s
693