UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 767

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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UBRT3
Set the number of receive FIFO receive data to be the trigger.
Each time data of the specified number has been stored from the receive shift
register to receive FIFO, the INTUBTIR interrupt is generated.
In the pending mode (UBFIC0.UBIRM bit = 0), the INTUBTIR signal is generated
under the conditions of the pending mode.
In the pointer mode (UBFIC0.UBIRM bit = 1), the number of receive data set as
the trigger can be only 1 byte (UBRT3 to UBRT0 bits = 0000), and other settings
are prohibited. If a setting of other than 1 byte is made, the operation is not
guaranteed.
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE B (UARTB)
UBRT2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
UBRT1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
UBRT0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
User’s Manual U18279EJ3V0UD
transmit FIFO set as trigger
1 byte
2 bytes
3 bytes
4 bytes
5 bytes
6 bytes
7 bytes
8 bytes
9 bytes
10 bytes
11 bytes
12 bytes
13 bytes
14 bytes
15 bytes
16 bytes
Number of data of
Pointer mode Pending mode
Settable
Setting
prohibited
Settable
(2/2)
765