UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 98

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

96
(3) System status register (SYS)
Status flags that indicate the operation status of the overall system are allocated to this register.
If this register is not written in the correct sequence including an access to the PRCMD register, data is not
written to the intended register, a protection error occurs, and the PRERR flag is set. This register is cleared
by writing “0” to it by an instruction from CPU.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
The PRERR flag operates under the following conditions.
(a) Set condition (PRERR flag = 1)
(b) Clear condition (PRERR flag = 0)
Cautions 1. If 0 is written to the SYS.PRERR bit which is not a special register, immediately after a
• When data is written to a special register without writing anything to the PRCMD register (when <3> is
• When data is written to an on-chip peripheral I/O register other than a special register (including
Remark
(i) When 0 is written to the SYS.PRERR flag
(ii) When the system is reset
executed without executing <2> in 3.4.8 (1) Setting data to special registers)
execution of a bit manipulation instruction) after writing data to the PRCMD register (if <3> in 3.4.8 (1)
Setting data to special registers is not the setting of a special register)
After reset:
SYS
2. If data is written to the PRCMD register, which is not a special register, immediately after
write access to the PRCMD register, the PRERR bit is cleared to 0 (the write access takes
precedence).
a write access to the PRCMD register, the PRERR bit is set to 1.
Even if an on-chip peripheral I/O register is read (excluding execution of a bit manipulation
instruction) between a write access to the PRCMD register and a write access to a special
register (such as an access to the internal RAM), the PRERR flag is not set and data can be
written to the special register.
PRERR
00H
0
1
0
Protection error did not occur.
Protection error occurred.
R/W
0
Address:
CHAPTER 3 CPU FUNCTION
User’s Manual U18279EJ3V0UD
0
FFFFF802H
Protection error detection
0
0
0
0
PRERR
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