UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 739

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

<R>
<R>
14.6.7 Receive data noise filter
rate generator.
as the input data. Therefore, data not exceeding 1 clock cycle width is judged to be noise and is not delivered to the
internal circuit (see Figure 14-11). See 14.7 (1) (a) Base clock regarding the base clock.
delayed by 3 clocks in relation to the external signal status.
Base clock (f
This filter samples signals received via the RXDAn pin using the base clock (f
When the same sampling value is read twice, the match detector output changes and the RXDAn signal is sampled
Moreover, since the circuit is as shown in Figure 14-10, the processing that goes on within the receive operation is
Remark
Internal signal A
Internal signal B
Internal signal C
RXDAn (input)
RXDAn
Base clock
UCLK
n = 0 to 2
(f
)
UCLK
)
In
CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE A (UARTA)
Q
Figure 14-11. Timing of RXDAn Signal Judged as Noise
Internal signal A
Figure 14-10. Noise Filter Circuit
User’s Manual U18279EJ3V0UD
Match
In
Q
(judged as noise)
Mismatch
Internal signal B
detector
Match
UCLK
Match
) supplied by the dedicated baud
In
LD_EN
Q
(judged as noise)
Mismatch
Internal signal C
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