UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 477

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(2) Operation timing in one-shot pulse output mode
External trigger input
INTTTEQCm0 signal
INTTTEQCm1 signal
TTmCCR0 register
TTmCCR1 register
(EVTTm pin input)
TOTm0 pin output
TOTm1 pin output
(a) Note on rewriting TTmCCRa register
16-bit counter
If the value of the TTmCCRa register is rewritten to a smaller value during counting, the 16-bit counter may
overflow. When an overflow may occur, stop counting and then change the set value.
When the TTmCCR0 register is rewritten from D
D
greater than D
greater than D
and compared with the count value. The counter counts up to FFFFH and then counts up again from
0000H. When the count value matches D
the TOTm1 pin. When the count value matches D
deasserts the TOTm1 pin, and stops counting.
Therefore, the counter may output a pulse with a delay period or active period different from that of the
one-shot pulse that is originally expected.
Remark
TTmCE bit
00
> D
FFFFH
0000H
01
and D
V850E/IF3: m = 1, a = 0, 1
V850E/IG3: m = 0, 1, a = 0, 1
01
11
10
and less than D
and less than D
> D
CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT)
11
, if the TTmCCR1 register is rewritten when the count value of the 16-bit counter is
Delay
(D
10
D
)
10
Active level width
(D
00
00
User’s Manual U18279EJ3V0UD
10
, each set value is reflected as soon as the register has been rewritten
D
− D
00
and if the TTmCCR0 register is rewritten when the count value is
10
+ 1)
D
10
11
, the counter generates the INTTTEQCm1 signal and asserts
D
Delay
(D
00
00
10
D
)
10
to D
Active level width
(D
01
00
D
01
, the counter generates the INTTTEQCm0 signal,
− D
00
and the TTmCCR1 register from D
10
+ 1)
D
10
Delay
(10000H + D
D
00
11
)
D
D
D
Active level width
(D
11
11
01
D
01
01
− D
10
11
to D
+ 1)
11
where
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