UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 67

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(2) NMI status saving registers (FEPC, FEPSW)
(3) Interrupt source register (ECR)
FEPSW
31 to 16
15 to 0
Bit position
FEPC
There are two NMI status saving registers, FEPC and FEPSW.
Upon occurrence of a non-maskable interrupt (NMI), the contents of the program counter (PC) are saved to
FEPC and the contents of the program status word (PSW) are saved to FEPSW.
The address of the next instruction following the instruction executed when a non-maskable interrupt occurs is
saved to FEPC, except for some instructions.
The current PSW contents are saved to FEPSW.
Since there is only one set of NMI status saving registers, the contents of these registers must be saved by the
program when multiple interrupt servicing is enabled.
Bits 31 to 26 of FEPC and bits 31 to 8 of FEPSW are reserved (fixed to 0) for future function expansion.
When the RETI instruction has been executed, the values of FEPC and FEPSW are restored to the PC and
PSW, respectively.
Upon occurrence of an interrupt or an exception, the interrupt source register (ECR) holds the source of an
interrupt or an exception. The value held by ECR is the exception code coded for each interrupt source. This
register is a read-only register, and thus data cannot be written to it using the LDSR instruction.
ECR
31
31
0
0
31
FECC
EICC
Bit name
0
0
0 0 0 0
0 0 0 0
26 25
Non-maskable interrupt (NMI) exception code
Exception, maskable interrupt exception code
0
FECC
0
0 0 0 0
CHAPTER 3 CPU FUNCTION
User’s Manual U18279EJ3V0UD
0
0
0 0 0 0
(PC contents saved)
16 15
0
0
Description
0 0 0 0
EICC
8
(PSW contents saved)
7
0
0
0
(x: Undefined)
(x: Undefined)
000000xxH
0xxxxxxxH
00000000H
After reset
After reset
After reset
65