UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 997

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

20.3.2 Restore
of the restored PC.
Recovery from maskable interrupt servicing is carried out by the RETI instruction.
When the RETI instruction is executed, the CPU performs the following steps, and transfers control to the address
<1> Loads the values of the PC and the PSW from EIPC and EIPSW because the PSW.EP bit is 0 and the
<2> Transfers control to the address of the restored PC and PSW.
The processing of the RETI instruction is shown below.
Note For the ISPR register, see 20.3.6 In-service priority register (ISPR).
Caution When the EP and NP bits are changed by the LDSR instruction during non-maskable interrupt
Remark
PSW.NP bit is 0.
servicing, in order to restore the PC and PSW correctly during recovery by the RETI
instruction, it is necessary to set EP back to 0 and NP back to 1 using the LDSR instruction
immediately before the RETI instruction.
The solid line shows the CPU processing flow.
1
PC
PSW
Corresponding
bit of ISPR
CHAPTER 20 INTERRUPT/EXCEPTION PROCESSING FUNCTION
Restores original processing
RETI instruction
Note
Figure 20-5. RETI Instruction Processing
PSW.EP
PSW.NP
0
0
EIPC
EIPSW
0
User’s Manual U18279EJ3V0UD
1
PC
PSW
FEPC
FEPSW
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