UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 104

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

102
Output mode
(PMnm = 0)
Input mode
(PMnm = 1)
(1) Port n register (Pn)
Setting of PMn Register
Notes 1. The value written to the output latch is retained until a new value is written to the output latch.
Data is input from or output to an external device by writing or reading the Pn register.
The Pn register consists of a port latch that holds output data, and a circuit that reads the status of pins.
Each bit of the Pn register corresponds to one pin of port n, and can be read or written in 1-bit units.
Data is written to or read from the Pn register as follows, regardless of the setting of the PMCn register.
2. Also, the value of the Pn register is read when the PMn register is in the output mode while the
3. If the PMn register is in the input mode while the alternate function is set, the statuses of the pins at that
alternate function is set.
time are read regardless of whether the alternate function is an input or output function.
Pn
After reset: Undefined
Pnm
Pn7
0
1
7
Data is written to the output latch
In the port mode (PMCn = 0), the contents of the
output latch are output from the pins.
Data is written to the output latch.
The pin status is not affected
Output 0.
Output 1.
Pn6
6
Table 4-5. Writing/Reading Pn Register
CHAPTER 4 PORT FUNCTIONS
Writing to Pn Register
Pn5
User’s Manual U18279EJ3V0UD
5
R/W
Control of output data (in output mode)
Note 1
Pn4
7
.
Note 1
.
Pn3
3
Pn2
2
The value of the output latch is read
The pin status is read
Pn1
1
Reading from Pn Register
Pn0
0
Note 3
.
Note 2
.