UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 583

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

10.4.4 Operation to rewrite register with transfer function
has a buffer register.
The following seven registers are provided with a transfer function and used to control a motor. Each of registers
• TABnCCR0: Register that specifies the cycle of the 16-bit counter (TAB)
• TABnCCR1: Register that specifies the duty factor of TOBnT1 (U) and TOBnB1 (U)
• TABnCCR2: Register that specifies the duty factor of TOBnT2 (V) and TOBnB2 (V)
• TABnCCR3: Register that specifies the duty factor of TOBnT3 (W) and TOBnB3 (W)
• TABnOPT1: Register that specifies the culling of interrupts
• TAAnCCR0: Register that specifies the A/D conversion start trigger generation timing (TAAn during tuning
• TAAnCCR1: Register that specifies the A/D conversion start trigger generation timing (TAAn during tuning
The following three rewrite modes are provided in the registers with a transfer function.
• Anytime rewriting mode
• Batch rewrite mode (transfer mode)
• Intermittent batch rewrite mode (transfer culling mode)
This mode is specified by setting the TABnOPT0.TABnCMS bit to 1. The setting of the TABnOPT2.TABnRDE bit
is ignored.
In this mode, each compare register is updated independently, and the value of the compare register is updated
as soon as a new value is written to it.
This mode is specified by setting the TABnOPT0.TABnCMS bit to 0, the TABnOPT1.TABnID4 to
TABnOPT1.TABnID0 bits to 00000, and the TABnOPT2.TABnRDE bit to 0.
When data is written to the TABnCCR1 register, the seven registers are transferred to the buffer register all at
once at the next transfer timing. Unless the TABnCCR1 register is rewritten, the transfer operation is not
performed even if the other six registers are rewritten.
The transfer timing is the timing of each crest (match between the 16-bit counter value and TABnCCR0 register
value) and valley (match between the 16-bit counter value and 0001H) regardless of the interrupt.
This mode is specified by setting the TABnOPT0.TABnCMS bit to 0 and the TABnOPT2.TABnRDE bit to 1.
When data is written to the TABnCCR1 register, the seven registers are transferred to the buffer register all at
once at the next transfer timing. Unless the TABnCCR1 register is rewritten, the transfer operation is not
performed even if the other six registers are rewritten.
If interrupt culling is specified by the TABnOPT1 register, the transfer timing is also culled as the interrupts are
culled, and the seven registers are transferred all at once at the culled timing of crest interrupt (match between
the 16-bit counter value and TABnCCR0 register value) or valley interrupt (match between the 16-bit counter
value and 0001H).
For details of the interrupt culling function, see 10.4.3 Interrupt culling function.
operation)
operation)
CHAPTER 10 MOTOR CONTROL FUNCTION
User’s Manual U18279EJ3V0UD
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