UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 489

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

• Compare operation
When the TTnCE bit is set to 1, 16-bit timer/event counter T starts counting, and the output signal of the TOTma
pin is inverted. When the count value of the 16-bit counter later matches the set value of the TTnCCRa register,
a compare match interrupt request signal (INTTTEQCna) is generated, and the output signal of the TOTna pin is
inverted.
The 16-bit counter continues counting in synchronization with the count clock. When it counts up to FFFFH, it
generates an overflow interrupt request signal (INTTTIOVn) at the next clock, is cleared to 0000H, and continues
counting. At this time, the overflow flag (TTnOPT0.TTnOVF bit) is also set to 1. Confirm that the overflow flag is
set to 1 and then clear it to 0 by executing the CLR instruction via software.
The TTnCCRa register can be rewritten while the counter is operating. If it is rewritten, the new value is reflected
at that time by anytime write, and compared with the count value.
Remark
INTTTEQCn0 signal
INTTTEQCn1 signal
TTnCCR0 register
TTnCCR1 register
TOTm0 pin output
TOTm1 pin output
INTTTIOVn signal
16-bit counter
V850E/IF3: n = 0, 1, m = 1, a = 0, 1
V850E/IG3: n = 0, 1, m = 0, 1, a = 0, 1
TTnOVF bit
TTnCE bit
Figure 8-34. Basic Timing in Free-Running Timer Mode (Compare Function)
FFFFH
0000H
CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT)
D
10
D
00
D
User’s Manual U18279EJ3V0UD
10
Cleared to 0 by
CLR instruction
D
00
D
10
D
00
CLR instruction
Cleared to 0 by
D
11
D
01
CLR instruction
Cleared to 0 by
D
11
D
D
D
01
01
11
CLR instruction
Cleared to 0 by
D
11
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