UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 513

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

8.6.9
to TTmMD0 bits = 1000)).
The encoder count function includes an encoder compare mode (see 8.6.10 Encoder compare mode (TTmMD3
(1) Count-up/-down control
(2) Setting initial value of 16-bit counter
(3) Basic operation
(4) Clear operation
Counting up or down by the 16-bit counter is controlled by the phase of input encoder signals (TENCm0 and
TENCm1) and setting of the TTmCTL2.TTmUDS1 and TTmCTL2.TTmUDS0 bits.
When the encoder count function is used, the internal count clock and external event count input (EVTTm)
cannot be used. Set the TTmCTL0.TTmCKS2 to TTmCTL0.TTmCKS0 bits to 000 and the TTmCTL1.TTmEEE
bit to 0.
The initial count value set to the TTmTCW register when the TTmCTL2.TTmECC bit = 0 is transferred to the
16-bit counter immediately after the counter starts its operation (TTmCTL0.TTmCE bit = 0 → 1), and the
counter starts the operation after it detects the valid edge of the encoder input signal (TENCm0 or TENCm1).
The TTmCCRa register generates a compare match interrupt request signal (INTTTEQCma) when the count
value of the 16-bit counter matches the value of the CCRa buffer register.
The 16-bit counter is cleared when the following conditions are satisfied in the encoder compare mode.
• When the value of the 16-bit counter matches the value of the compare register (the TTmCTL2.TTmECM1
• When the edge of the encoder clear input signal (TECRm) is detected and cleared (the TTmECS1 and
• When the clear level condition of the TENCm0, TENCm1, and TECRm pins is detected (the TTmZCL,
Remark
Encoder count function
and TTmCTL2.TTmECM0 bits are set)
TTmECS0 bits are set when the TTmIOC3.TTmSCE bit = 0)
TTmBCL, and TTmACL bits are set when the TTmSCE bit = 1)
Encoder compare mode
V850E/IF3: m = 1, a = 0, 1
V850E/IG3: m = 0, 1, a = 0, 1
CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT)
Mode
User’s Manual U18279EJ3V0UD
Compare only
TTmCCR0 Register
Compare only
TTmCCR1 Register
511