UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 995

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

20.3 Maskable Interrupts
have 95 maskable interrupt sources.
according to the default priority. In addition to the default priority, eight levels of priorities can be specified by using
the interrupt control registers (programmable priority control).
signals is disabled and the interrupt disabled (DI) status is set.
enables servicing of interrupts having a higher priority than the interrupt request signal in progress (specified by the
interrupt control register). Note that only interrupts with a higher priority will have this capability; interrupts with the
same priority level cannot be serviced as multiple interrupts.
the EI instruction, and execute the DI instruction before the RETI instruction to restore the original values of EIPC and
EIPSW.
20.3.1 Operation
routine.
signal generated while another interrupt is being serviced (while PSW.NP bit = 1 or ID bit = 1) are held pending inside
the INTC. In this case, servicing a new maskable interrupt is started in accordance with the priority of the pending
maskable interrupt request signal if either the maskable interrupt is unmasked or NP and ID bits are cleared to 0 by
using the RETI or LDSR instruction.
Maskable interrupt request signals can be masked by interrupt control registers. The V850E/IF3 and V850E/IG3
If two or more maskable interrupt request signals are generated at the same time, they are acknowledged
When an interrupt request signal has been acknowledged, the acknowledgment of other maskable interrupt request
When the EI instruction is executed in an interrupt service routine, the interrupt enabled (EI) status is set, which
To enable multiple interrupt servicing, however, save EIPC and EIPSW to memory or registers before executing
If a maskable interrupt occurs, the CPU performs the following processing, and transfers control to the handler
<1> Saves the restored PC to EIPC.
<2> Saves the current PSW to EIPSW.
<3> Writes an exception code to the lower halfword of ECR (EICC).
<4> Sets the PSW.ID bit to 1 and clears the PSW.EP bit to 0.
<5> Sets the handler address corresponding to each interrupt to the PC, and transfers control.
The maskable interrupt request signal masked by interrupt controller (INTC) and the maskable interrupt request
How maskable interrupts are serviced is illustrated below.
CHAPTER 20 INTERRUPT/EXCEPTION PROCESSING FUNCTION
User’s Manual U18279EJ3V0UD
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