UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 539

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

9.3
(1) TMMn control register 0 (TMnCTL0)
Control Register
The TMnCTL0 register is an 8-bit register that controls the TMMn operation.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
The same value can always be written to the TMnCTL0 register by software.
Cautions 1. Set the TMnCKS2 to TMnCKS0 bits when the TMnCE bit = 0.
Remark
(n = 0 to 3)
TMnCTL0
2. Be sure to clear bits 3 to 6 to “0”.
f
XX
After reset: 00H
: Peripheral clock frequency
However, when changing the value of the TMnCE bit from 0 to 1, it is impossible to set
the value of the TMnCKS2 to TMnCKS0 bits simultaneously.
TMnCKS2
The internal clock control and internal circuit reset for TMMn are performed
asynchronously with the TMnCE bit. When the TMnCE bit is cleared to 0, the
internal clock of TMMn is stopped (fixed to low level) and 16-bit counter is reset
asynchronously.
TMnCE
TMnCE
<7>
0
1
0
0
0
0
1
1
1
1
CHAPTER 9 16-BIT INTERVAL TIMER M (TMM)
TMnCKS1
TMMn operation disabled (16-bit counter reset asynchronously)
R/W
TMMn operation enabled. Start operation clock supply. Start TMMn
operation.
6
0
0
0
1
1
0
0
1
1
Address: TM0CTL0 FFFFF540H, TM1CTL0 FFFFF550H,
User’s Manual U18279EJ3V0UD
TMnCKS0
Internal clock operation enable/disable specification
5
0
0
1
0
1
0
1
0
1
TM2CTL0 FFFFF560H, TM3CTL0 FFFFF570H
f
f
f
f
f
f
f
f
XX
XX
XX
XX
XX
XX
XX
XX
/2
/4
/8
/16
/64
/256
/1024
/2048
4
0
3
0
Count clock selection
TMnCKS2 TMnCKS1 TMnCKS0
2
1
0
537