UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 78

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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(3) On-chip peripheral I/O area
(4) External memory area (
4 KB of memory, addresses FFFF000H to FFFFFFFH, is provided as an on-chip peripheral I/O area.
An image of addresses FFFF000H to FFFFFFFH can be seen at addresses 3FFF000H to 3FFFFFFH
Note Addresses 3FFF000H to 3FFFFFFH are access-prohibited. To access the on-chip peripheral I/O,
On-chip peripheral I/O registers associated with the operating mode specification and the state monitoring for
the on-chip peripheral I/O are all memory-mapped to the on-chip peripheral I/O area. Program fetches cannot
be executed from this area.
Cautions 1. In the V850E/IF3 and V850E/IG3, if a register is word accessed, halfword access is
3 MB (0100000H to 03FFFFFH) are available for the external memory area. For details, see CHAPTER 18
BUS CONTROL FUNCTION.
specify addresses FFFF000H to FFFFFFFH.
2. For registers in which byte access is possible, if halfword access is executed, the higher
3. Addresses that are not defined as registers are reserved for future expansion. If these
performed twice in the order of lower address, then higher address of the word area,
disregarding the lower 2 bits of the address.
8 bits become undefined during the read operation, and the lower 8 bits of data are
written to the register during the write operation.
addresses are accessed, the operation is undefined and not guaranteed.
Addresses 3FFF000H to 3FFFFFFH cannot be specified as the source/destination
address of DMA transfer. Be sure to use addresses FFFF000H to FFFFFFFH for the
source/destination address of DMA transfer.
μ
PD70F3454GC-8EA-A and 70F3454F1-DA9-A only)
Figure 3-9. On-Chip Peripheral I/O Area
F F F F F F F H
F F F F 0 0 0 H
CHAPTER 3 CPU FUNCTION
User’s Manual U18279EJ3V0UD
On-chip peripheral I/O area
(4 KB)
Note
.