UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 640

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

638
(9) A/Dn conversion result extension registers 0 to 4, 0H to 4H (ADnECR0 to ADnECR4, ADnECR0H to
Remark
ADnECR4H)
The ADnECRa and ADnECRaH registers hold the result of A/D conversion in their higher 12 bits and indicate
the status (information on the A/D conversion result of the analog input pin specified by the
ADnCHx.ADnTRGCHx2 to ADnTRGCHx0 bits or ADnTRGCHx6 to ADnTRGCHx4 bits) of the A/D conversion
result with the lower 1 bit in the extension buffer mode. Five of these registers are provided per circuit and two
circuits are available.
conversion result extension buffer register a.
conversion result is shifted from A/Dn conversion result extension buffer registers 0 to 2 to the higher 12 bits of
the ADnECR0 to ADnECR2 registers and stored. Bits 1 to 3 are always 0 when read. When selection load
trigger 2 is generated, the A/D conversion result is shifted from the A/Dn conversion result extension buffer
registers 3 and 4 to the higher 12 bits of the ADnECR3 and ADnECR4 registers and stored. Bits 1 to 3 are
always 0 when read.
The higher 8 bits of the A/D conversion result are read from the ADnECRaH register.
These registers are read-only in 16-bit or 8-bit units. To read the A/D conversion result in 16-bit units, specify
the ADnECRa register. Specify the ADnECRaH register to read the higher 8 bits of the A/D conversion result.
Reset sets these registers to 0000H.
While the result of A/D conversion is stored in the ADnECRa register, a read access to that register
is held pending. The pending read access is executed when storing the A/D conversion result is
completed. Similarly, storing the A/D conversion result in the ADnECRa register is held pending
while a read access is made to that register. The pending A/D conversion result is stored in the
register after the read access is completed.
When A/D conversion is completed, the A/D conversion result is stored in A/Dn
CHAPTER 12 A/D CONVERTERS 0 AND 1
User’s Manual U18279EJ3V0UD
When selection load trigger 1 is later generated, the A/D