UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 763

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(6) UARTB FIFO control register 0 (UBFIC0)
Note After transmit FIFO is cleared (UBTFC bit = 1), accessing the registers related to UARTB is prohibited
Remark
The UBFIC0 register is used to select the operation mode of UARTB and the functions that become valid in
the FIFO mode (UBMOD bit = 1). In the FIFO mode, it clears transmit FIFO/receive FIFO and specifies the
timing mode in which the transmission enable interrupt request signal (INTUBTIT)/reception end interrupt
request signal (INTUBTIR) is generated.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
for the duration of four cycles of f
reading the UBFIC0 register. If these registers are accessed, the operation is not guaranteed.
f
UBFIC0
XX
: Peripheral clock
After reset: 00H
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE B (UARTB)
UBMOD
UBMOD
UBTFC
•
•
•
The UBTFC bit is valid only in the FIFO mode (UBMOD bit = 1), and is invalid in
the single mode (UBMOD bit = 0).
When 1 is written to the UBTFC bit, the pointer to transmit FIFO is cleared to 0.
In the pending mode (UBITM bit = 0), the interrupt request signal (INTUBTIT)
held pending is cleared
register (UTIC) is not cleared to 0. Clear this bit to 0 as necessary.
When 0 is written to the UBTFC bit, the status is retained. No operation, such
as clearing or setting, is executed.
When writing 1 to the UBTFC bit, be sure to clear the UBCTL0.UBTXE bit to 0
(disabling transmission). If 1 is written to the UBTFC bit when the UBTXE bit is
1 (transmission enabled), the operation is not guaranteed.
0
1
0
1
7
Single mode
FIFO mode
Normal status
Clear (This bit automatically returns to 0 after transmit FIFO is cleared.)
R/W
6
0
XX
Address: FFFFFA4AH
User’s Manual U18279EJ3V0UD
or until clearing the UBTFC bit (automatic recovery) is confirmed by
5
0
Note
Specification of UARTB operation mode
. However, bit 7 (UTIF) of the interrupt control
Transmit FIFO clear trigger bit
4
0
UBTFC
3
UBRFC
2
UBITM
1
UBIRM
0
(1/2)
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