UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 526

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

524
INTTTEQCm0 signal
INTTTEQCm1 signal
INTTTEQCm0 signal
TTmUDS1 and TTmUDS0 Bits = 11, TECRm = High Level, TENCm1 = Low Level, and TENCm0 = High Level) (3/3)
(TENCm0 pin input)
(TENCm1 pin input)
(iv) If the high level is input to the TECRm pin later than the low level is input to the TENCm1 pin while
Encoder clear input
Remark
TTmCCR0 register
TTmCCR1 register
TTmCCR0 register
(TECRm pin input)
TTmCNT register
Figure 8-56. Operation Example (When TTmSCE Bit = 1, TTmZCL Bit = 1, TTmBCL Bit = 0, TTmACL Bit = 1,
Peripheral clock
the counter is counting up, the counter is cleared after it counts up.
Encoder input
Encoder input
timing signal
Clear signal
If the counter is cleared in this way, a miscount does not occur even if inputting the signal to the TECRm
pin is late, because the clear level condition of the TECRm, TENCm1, and TENCm0 pins is set and the 16-
bit counter is cleared to 0000H when the clear level condition is detected.
V850E/IF3: m = 1
V850E/IG3: m = 0, 1
Count
Compare match interrupt request signal is not generated.
N
CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT)
User’s Manual U18279EJ3V0UD
0000H (when TTmCCR1 register is set to 0000H)
N
N − 1 (when TTmCCR0 register is set to N − 1)
−
N (when TTmCCR0 register is set to N)
1
H
L
H
0000H