UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 834

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

832
(2) Operation timing
Caution In continuous transmission mode, the reception end interrupt request signal (INTCBnR) is not
Remark
INTCBnR signal
INTCBnT signal
CBnTSF bit
SCKBn pin
(1) Write 00H to the CBnCTL1 register, and select communication type 1, communication clock (f
(2) Write 00H to the CBnCTL2 register, and set the transfer data length to 8 bits.
(3) Write C3H to the CBnCTL0 register, and select the transmission mode, MSB first, and continuous
(4) The CBnSTR.CBnTSF bit is set to 1 by writing the transmit data to the CBnTX register, and
(5) When transmission is started, output the serial clock to the SCKBn pin, and output the transmit data
(6) When transfer of the transmit data from the CBnTX register to the shift register is ended and writing to
(7) To continue transmission, write the transmit data to the CBnTX register again after the INTCBnT signal
(8) When a new transmit data is written to the CBnTX register before communication end, the next
(9) The transfer of the transmit data from the CBnTX register to the shift register is ended and the
(10) When the next transmit data is not written to the CBnTX register before transfer end, stop the serial
(11) To release the transmission enable status, write the CBnCTL0.CBnPWR bit = 0 and the
SOBn pin
f
transfer mode at the same time as enabling the operation of the communication clock (f
transmission is started.
from the SOBn pin in synchronization with the serial clock.
the CBnTX register is enabled, the transmission enable interrupt request signal (INTCBnT) is
generated.
is generated.
communication is started following communication end.
INTCBnT signal is generated. To end continuous transmission at the current transmission, do not
write to the CBnTX register.
clock output to the SCKBn pin after transfer end, and clear the CBnTSF bit to 0.
CBnCTL0.CBnTXE bit = 0 after checking that the CBnTSF bit = 0.
XX
generated.
n = 0 to 2
/4, and master mode.
L
(1)
(2)
(3)
(4)
(5)
Bit 7
(6)
Bit 6
CHAPTER 16 CLOCKED SERIAL INTERFACE B (CSIB)
Bit 5
Bit 4
(7)
Bit 3
User’s Manual U18279EJ3V0UD
Bit 2
Bit 1
Bit 0
(8) (9)
Bit 7
Bit 6
Bit 5 Bit 4
Bit 3
Bit 2
Bit 1
(10)
Bit 0
CCLK
(11)
).
CCLK
) =