UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 380

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

378
• Compare operation
When the TABnCE bit is set to 1, 16-bit timer/event counter AB starts counting, and the output signals of the
TOBn0 to TOBn3 pins are inverted. When the count value of the 16-bit counter later matches the set value of
the TABnCCRa register, a compare match interrupt request signal (INTTBnCCa) is generated, and the output
signals of the TOBn0 to TOBn3 pins are inverted.
The 16-bit counter continues counting in synchronization with the count clock. When it counts up to FFFFH, it
generates an overflow interrupt request signal (INTTBnOV) at the next clock, is cleared to 0000H, and continues
counting. At this time, the overflow flag (TABnOPT0.TABnOVF bit) is also set to 1. Confirm that the overflow
flag is set to 1 and then clear it to 0 by executing the CLR instruction via software.
The TABnCCRa register can be rewritten while the counter is operating. If it is rewritten, the new value is
reflected at that time, and compared with the count value.
Remark
Remark
TABnCCR0 register
TABnCCR1 register
TABnCCR2 register
TABnCCR3 register
INTTBnCC0 signal
INTTBnCC1 signal
INTTBnCC2 signal
INTTBnCC3 signal
TOBn0 pin output
TOBn1 pin output
TOBn2 pin output
TOBn3 pin output
INTTBnOV signal
a = 0 to 3
n = 0, 1
n = 0, 1
16-bit counter
TABnOVF bit
Figure 7-33. Basic Timing in Free-Running Timer Mode (Compare Function)
TABnCE bit
FFFFH
0000H
CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB)
D
D
10
10
D
20
D
User’s Manual U18279EJ3V0UD
30
D
00
D
20
CLR instruction
Cleared to 0 by
D
30
D
D
00
11
D
20
D
30
D
00
CLR instruction
Cleared to 0 by
D
11
D
11
D
21
D
31
D
D
01
21
D
31
Cleared to 0 by
CLR instruction
D
01
D
11
D
21
D
31
D
01