UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 421

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(8) TMTn option register 0 (TTnOPT0)
Note In the V850E/IF3, this bit can be set only in TMT1. Be sure to set bits 4 and 5 of TMT0 to “0”.
Cautions 1. Rewrite the TTmCCS1 and TTmCCS0 bits when the TTmCE bit = 0. (The same value can be
The TTnOPT0 register is an 8-bit register that sets the capture/compare operation and detects overflow.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
2. Be sure to set bits 1 to 3, 6, and 7 to “0”.
V850E/IF3
V850E/IG3
TTnOPT0
n = 0, 1
m = 1
n = 0, 1
m = 0, 1
written when the TTmCE bit = 1.) If rewriting was mistakenly performed, clear the TTmCE
bit to 0 and then set these bits again.
After reset: 00H
TTmCCS1
TTmCCS0
Set (1)
Reset (0)
The TTmCCS1 bit setting is valid only in the free-running timer mode.
The TTmCCS0 bit setting is valid only in the free-running timer mode.
• The TTnOVF bit is set to 1 when the 16-bit counter value overflows from FFFFH
• An overflow interrupt request signal (INTTTIOVn) is generated at the same time
• The TTnOVF bit is not cleared to 0 even when the TTnOVF bit or the TTnOPT0
• Before clearing the TTnOVF bit to 0 after generation of the INTTTIOVn signal, be
• The TTnOVF bit can be both read and written, but the TTnOVF bit cannot be set
to 0000H in the free-running timer mode or the pulse width measurement mode.
that the TTnOVF bit is set to 1. The INTTTIOVn signal is not generated in modes
other than the free-running timer mode and the pulse width measurement mode.
register are read when the TTnOVF bit = 1.
sure to confirm (by reading) that the TTnOVF bit is set to 1.
to 1 by software. Writing 1 has no effect on the operation of TMTn.
0
1
0
1
CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT)
7
0
TTnOVF
Note
Note
R/W
Compare register selected
Capture register selected (cleared by the TTmCTL0.TTmCE bit = 0)
Compare register selected
Capture register selected (cleared by the TTmCTL0.TTmCE bit = 0)
6
0
Address: TT0OPT0 FFFFF587H, TT1OPT0 FFFFF5C7H
User’s Manual U18279EJ3V0UD
TTmCCS1
Overflow occurred
0 written to TTnOVF bit or TTnCTL0.TTnCE bit = 0
TTmCCR1 register capture/compare selection
TTmCCR0 register capture/compare selection
5
Note
TTmCCS0
TMTn overflow detection flag
4
Note
3
0
2
0
1
0
TTnOVF
<0>
419