UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 366

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

364
(2) Operation timing in one-shot pulse output mode
External trigger input
TABnCCR0 register
TABnCCRb register
INTTBnCC0 signal
INTTBnCCb signal
(TRGBn pin input)
TOBn0 pin output
TOBnb pin output
(a) Note on rewriting TABnCCRa register
16-bit counter
TABnCE bit
To change the set value of the TABnCCRa register to a smaller value, stop counting once, and then
change the set value. When the overflow may occur, stop counting once, and then change the set value.
When the TABnCCR0 register is rewritten from D
where D
counter is greater than D
value is greater than D
rewritten and compared with the count value. The counter counts up to FFFFH and then counts up again
from 0000H. When the count value matches D
asserts the TOBnb pin. When the count value matches D
deasserts the TOBnb pin, and stops counting.
Therefore, the counter may output a pulse with a delay period or active period different from that of the
one-shot pulse that is originally expected.
Remark
FFFFH
0000H
00
n = 0, 1, a = 0 to 3, b = 1 to 3
> D
01
and D
CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB)
Delay
(D
01
b0
b0
)
Active level width
b1
and less than D
> D
D
(D
b0
and less than D
0
b1
− D
D
, if the TABnCCRb register is rewritten when the count value of the 16-bit
b0
D
b0
User’s Manual U18279EJ3V0UD
D
00
+ 1)
00
00
, each set value is reflected as soon as the register has been
b0
(10000H + D
and if the TABnCCR0 register is rewritten when the count
D
b0
Delay
b1
00
, the counter generates the INTTBnCCb signal and
to D
01
D
b1
01
00
)
, the counter generates the INTTBnCC0 signal,
and the TABnCCRb register from D
Active level width
(D
D
01
b1
− D
D
b1
b1
+ 1)
D
01
D
01
Delay
(D
b1
D
)
Active level width
b1
(D
01
− D
D
b1
01
b0
+ 1)
to D
b1