UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 460

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

16-bit counter is cleared from FFFFH to 0000H, starts counting at the same time, and outputs a PWM waveform from
the TOTm1 pin. If the trigger is generated again while the counter is operating, the counter is cleared to 0000H and
restarted. (The output of the TOTm0 pin is inverted. The TOTm1 pin outputs a high-level regardless of the status
(high/low) when a trigger occurs.)
count value matches the value of the CCR0 buffer register, and the 16-bit counter is cleared to 0000H. The compare
match interrupt request signal (INTTTEQCm1) is generated when the count value of the 16-bit counter matches the
value of the CCR1 buffer register.
counter matches the value of the CCRa buffer register and the 16-bit counter is cleared to 0000H.
used as the trigger.
458
16-bit timer/event counter T waits for a trigger when the TTmCE bit is set to 1. When the trigger is generated, the
The active level width, cycle, and duty factor of the PWM waveform can be calculated as follows.
The compare match request signal (INTTTEQCm0) is generated when the 16-bit counter counts next time after its
The value set to the TTmCCRa register is transferred to the CCRa buffer register when the count value of the 16-bit
The valid edge of an external trigger input (EVTTm), or setting the software trigger (TTmCTL1.TTmEST bit) to 1 is
Remark
External trigger input
INTTTEQCm0 signal
INTTTEQCm1 signal
TTmCCR0 register
TTmCCR1 register
(EVTTm pin input)
TOTm0 pin output
TOTm1 pin output
Active level width = (Set value of TTmCCR1 register) × Count clock cycle
Cycle = (Set value of TTmCCR0 register + 1) × Count clock cycle
Duty factor = (Set value of TTmCCR1 register)/(Set value of TTmCCR0 register + 1)
16-bit counter
TTmCE bit
V850E/IF3: m = 1, a = 0, 1
V850E/IG3: m = 0, 1, a = 0, 1
FFFFH
0000H
Figure 8-22. Basic Timing in External Trigger Pulse Output Mode
trigger
Wait
for
CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT)
Active level
width (D
Cycle (D
D
1
1
)
D
0
User’s Manual U18279EJ3V0UD
0
+ 1)
Active level
width (D
Cycle (D
D
1
1
)
D
0
0
+ 1)
D
D
0
1
D
1
D
0
Active level
width (D
Cycle (D
D
1
1
)
D
0
0
+ 1)