UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 663

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

12.4.5 Operation of 1-channel conversion
conversion is stored in the ADnCRk register corresponding to the ANInk pin. The ANInk pin and ADnCRk register
correspond to each other on a one-to-one basis, and an A/Dn conversion end interrupt request signal (INTADn) is
generated each time conversion has been completed.
polling mode. In the hardware trigger mode, the A/D converter waits for a trigger.
The signal of one analog input pin (ANInk) specified by the ADnCHEN register is converted. The result of
After completion of A/D conversion, the conversion operation is stopped in the A/D trigger mode or A/D trigger
Remark
Software processing
Figure 12-12. Operation of 1-Channel Conversion (in A/D Trigger Mode): A/D Converter 0
AD0CR1 register
INTAD0 interrupt
A/D conversion
A/D converter 0: n = 0, k = 0 to 5
A/D converter 1: n = 1, k = 0 to 7
ANI01 (input)
AD0CS bit
Analog input pin
ANI00
ANI01
ANI02
ANI03
ANI04
ANI05
start AD0CE
Conversion
bit set
Data 1
(ANI01)
Data 1
CHAPTER 12 A/D CONVERTERS 0 AND 1
start AD0CE
Conversion
(ANI01)
bit set
Data 1
Data 2
(ANI01)
Data 2
start AD0CE
Conversion
User’s Manual U18279EJ3V0UD
(ANI01)
bit set
Data 2
Data 3
(ANI01)
Data 3
A/D converter 0
start AD0CE
Conversion
(ANI01)
bit set
Data 3
Data 4
(ANI01)
Data 4
end AD0CE
Conversion
bit clear
(ANI01)
Data 4
AD0CRn register
start AD0CE
Conversion
bit set
AD0CR0
AD0CR1
AD0CR2
AD0CR3
AD0CR4
AD0CR5
Data 5
(ANI01)
Data 5
Conversion
end AD0CE
bit clear
(ANI01)
Data 5
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