UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 998

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

20.3.3 Priorities of maskable interrupts
being serviced. Multiple interrupts can be controlled by priority levels.
programmable priority levels that are specified by the interrupt priority level specification bit (xxPRn) of the interrupt
control register (xxICn). When two or more interrupts having the same priority level specified by the xxPRn bit are
generated at the same time, interrupts are serviced in order depending on the priority level allocated to each interrupt
request signal type (default priority level) beforehand. For more information, see Table 20-1 Interrupt Source List.
Programmable priority control customizes interrupt request signals into eight levels by the setting of the priority level
specification flag.
when multiple interrupts are to be used, clear the ID flag to 0 beforehand (for example, by placing the EI instruction in
the interrupt servicing program) to set the interrupt enabled mode.
996
The INTC provides multiple interrupt servicing in which an interrupt is acknowledged while another interrupt is
There are two types of priority level control: control based on the default priority levels, and control based on the
Note that when an interrupt request signal is acknowledged, the PSW.ID flag is automatically set to 1. Therefore,
Remark
xx: Identification name of each peripheral unit (see Table 20-2)
n: Peripheral unit number (see Table 20-2)
CHAPTER 20 INTERRUPT/EXCEPTION PROCESSING FUNCTION
User’s Manual U18279EJ3V0UD