UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 822

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UPD70F3451GC-UBT-A

Manufacturer Part Number
UPD70F3451GC-UBT-A
Description
MCU 32BIT 128KB FLASH 80LQFP
Manufacturer
Renesas Electronics America
Series
V850E/Ix3r
Datasheet

Specifications of UPD70F3451GC-UBT-A

Core Processor
RISC
Core Size
32-Bit
Speed
64MHz
Connectivity
CSI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
44
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3.5 V ~ 5.5 V
Data Converters
A/D 10x12b, 4x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3451GC-UBT-A
Manufacturer:
Renesas Electronics America
Quantity:
10 000
820
INTCBnR signal
(2) Operation timing
Remark
CBnTSF bit
SCKBn pin
SOBn pin
(1) Write 00H to the CBnCTL1 register, and select communication type 1, communication clock (f
(2) Write 00H to the CBnCTL2 register, and set the transfer data length to 8 bits.
(3) Write C1H to the CBnCTL0 register, and select the transmission mode and MSB first at the same time
(4) The CBnSTR.CBnTSF bit is set to 1 by writing the transmit data to the CBnTX register, and
(5) When transmission is started, output the serial clock to the SCKBn pin, and output the transmit data
(6) When transmission of the transfer data length set with the CBnCTL2 register is completed, stop the
(7) To continue transmission, start the next transmission by writing the transmit data to the CBnTX register
(8) To end transmission, write the CBnCTL0.CBnPWR bit = 0 and the CBnCTL0.CBnTXE bit = 0.
f
as enabling the operation of the communication clock (f
transmission is started.
from the SOBn pin in synchronization with the serial clock.
serial clock output and transmit data output, generate the reception end interrupt request signal
(INTCBnR) at the last edge of the serial clock, and clear the CBnTSF bit to 0.
again after the INTCBnR signal is generated.
XX
n = 0 to 2
/4, and master mode.
(1)
(2)
(3)
(4)
(5)
Bit 7
Bit 6
CHAPTER 16 CLOCKED SERIAL INTERFACE B (CSIB)
Bit 5
Bit 4
Bit 3
User’s Manual U18279EJ3V0UD
Bit 2
Bit 1
(6)
Bit 0
(7)
CCLK
Bit 7 Bit 6
).
Bit 5
Bit 4
Bit 3 Bit 2
Bit 1
Bit 0
(8)
CCLK
) =

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