UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 350

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

348
TABnIOC2
(d) TABn I/O control register 2 (TABnIOC2)
(e) TABn counter read buffer register (TABnCNT)
(f) TABn capture/compare registers 0 to 3 (TABnCCR0 to TABnCCR3)
The value of the 16-bit counter can be read by reading the TABnCNT register.
If D
D
Remarks 1. TABn I/O control register 1 (TABnIOC1) and TABn option register 0 (TABnOPT0) are not
3
Cycle = (D
TOBn1 pin PWM waveform active level width = D
TOBn2 pin PWM waveform active level width = D
TOBn3 pin PWM waveform active level width = D
, to the TABnCCR3 register, the cycle and active level of the PWM waveform are as follows.
0
is set to the TABnCCR0 register, D
0
Figure 7-22. Setting of Registers in External Trigger Pulse Output Mode (3/3)
2. n = 0, 1
0
+ 1) × Count clock cycle
used in the external trigger pulse output mode.
b = 1 to 3
0
CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB)
0
0
User’s Manual U18279EJ3V0UD
TABnEES1
1
0/1
to the TABnCCR1 register, D
TABnEES0 TABnETS1 TABnETS0
0/1
1
2
3
× Count clock cycle
× Count clock cycle
× Count clock cycle
0/1
0/1
2
to the TABnCCR2 register, and
Select valid edge of
external trigger input (TRGBn pin)
Select valid edge of
external event count input
(EVTBn pin)