UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 792

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

790
(4) Allowable baud rate range during reception
Maximum allowable
Minimum allowable
The degree to which a discrepancy from the transmission destination’s baud rate is allowed during reception
is shown below.
Caution The equations described below should be used to set the baud rate error during reception
As shown in Figure 15-10, after the start bit is detected, the receive data latch timing is determined according
to the counter that was set by the UBCTL2 register. If all data up to the final data (stop bit) is in time for this
latch timing, the data can be received normally.
Applying this to 11-bit reception is, theoretically, as follows.
FL = (Brate)
Minimum allowable value:
Brate: UARTB baud rate
k:
FL:
Latch timing margin: 2 clocks
UARTB
so that it always is within the allowable error range.
value
value
−
UBCTL2 set value
1-bit data length
1
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE B (UARTB)
Figure 15-10. Allowable Baud Rate Range During Reception
Latch timing
Start bit
Start bit
Start bit
FLmin
Bit 0
User’s Manual U18279EJ3V0UD
Bit 0
=
Bit 0
FL
11
×
FL
Bit 1
−
Bit 1
Bit 1
k
1 data frame (11 × FL)
2
−
k
FLmin
2
FLmax
×
FL
Bit 7
=
Bit 7
Bit 7
21
Parity bit
k
2
Parity bit
k
+
2
Parity bit
FL
Stop bit
Stop bit
Stop bit