UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 837

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(2) Operation timing
Remark
SIBn pin capture
INTCBnR signal
CBnSCE bit
CBnTSF bit
SCKBn pin
(1) Write 00H to the CBnCTL1 register, and select communication type 1, communication clock (f
(2) Write 00H to the CBnCTL2 register, and set the transfer data length to 8 bits.
(3) Write A3H to the CBnCTL0 register, and select the reception mode, MSB first, and continuous transfer
(4) The CBnSTR.CBnTSF bit is set to 1 by performing a dummy read of the CBnRX register, and
(5) When reception is started, output the serial clock to the SCKBn pin, and capture the receive data of
(6) When reception is ended, the reception end interrupt request signal (INTCBnR) is generated, and
(7) When the CBnCTL0.CBnSCE bit = 1 upon communication end, the next communication is started
(8) To end continuous reception at the current reception, write the CBnSCE bit = 0.
(9) Read the CBnRX register.
(10) When reception is ended, the INTCBnR signal is generated, and reading of the CBnRX register is
(11) Read the CBnRX register.
(12) If an overrun error occurs, write the CBnSTR.CBnOVE bit = 0, and clear the error flag.
(13) To release the reception enable status, write the CBnCTL0.CBnPWR bit = 0 and the
SOBn pin
SIBn pin
timing
f
mode at the same time as enabling the operation of the communication clock (f
reception is started.
the SIBn pin in synchronization with the serial clock.
reading of the CBnRX register is enabled.
following communication end.
enabled. When the CBnSCE bit = 0 is set before communication end, stop the serial clock output to
the SCKBn pin, and clear the CBnTSF bit to 0, to end the receive operation.
CBnCTL0.CBnRXE bit = 0 after checking that the CBnTSF bit = 0.
XX
n = 0 to 2
/4, and master mode.
L
(1)
(2)
(3)
(4)
(5)
Bit 7 Bit 6
CHAPTER 16 CLOCKED SERIAL INTERFACE B (CSIB)
Bit 5 Bit 4
Bit 3 Bit 2
User’s Manual U18279EJ3V0UD
Bit 1
(6) (7) (8) (9)
Bit 0
Bit 7 Bit 6
Bit 5 Bit 4
Bit 3 Bit 2
Bit 1
(10)
Bit 0
CCLK
).
(11) (13)
CCLK
) =
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