UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 840

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

838
(2) Operation timing
Remark
SIBn pin capture
INTCBnR signal
INTCBnT signal
CBnTSF bit
SCKBn pin
(1) Write 00H to the CBnCTL1 register, and select communication type 1, communication clock (f
(2) Write 00H to the CBnCTL2 register, and set the transfer data length to 8 bits.
(3) Write E3H to the CBnCTL0 register, and select the transmission/reception mode, MSB first, and
(4) The CBnSTR.CBnTSF bit is set to 1 by writing the transmit data to the CBnTX register, and
(5) When transmission/reception is started, output the serial clock to the SCKBn pin, output the transmit
(6) When transfer of the transmit data from the CBnTX register to the shift register is ended and writing to
(7) To continue transmission/reception, write the transmit data to the CBnTX register again after the
(8) When one transmission/reception is ended, the reception end interrupt request signal (INTCBnR) is
(9) When a new transmit data is written to the CBnTX register before communication end, the next
(10) Read the CBnRX register.
SOBn pin
SIBn pin
timing
f
continuous transfer mode at the same time as enabling the operation of the communication clock
(f
transmission/reception is started.
data to the SOBn pin in synchronization with the serial clock, and capture the receive data of the SIBn
pin.
the CBnTX register is enabled, the transmission enable interrupt request signal (INTCBnT) is
generated.
INTCBnT signal is generated.
generated, and reading of the CBnRX register is enabled.
communication is started following communication end.
XX
CCLK
n = 0 to 2
/4, and master mode.
(1)
(2)
(3)
).
(4)
(5)
Bit 7
Bit 7
CHAPTER 16 CLOCKED SERIAL INTERFACE B (CSIB)
Bit 6
Bit 6
(6)
Bit 5 Bit 4 Bit 3
Bit 5 Bit 4 Bit 3
(7)
User’s Manual U18279EJ3V0UD
Bit 2
Bit 2
Bit 1
Bit 1
(8) (9) (10) (11)
Bit 0
Bit 0 Bit 7
Bit 7
Bit 6
Bit 6
Bit 5 Bit 4 Bit 3
Bit 5 Bit 4 Bit 3
Bit 2
Bit 2
Bit 1
Bit 1
(12)
Bit 0
Bit 0
(13) (15)
CCLK
) =
(1/2)